System On A Chip

This paper will examine current methods used to eliminate waived errors at the chip level and describe a new automatable method for identifying and removing waived errors from DRC results.

This white paper discusses the conditions that have created the need for pattern matching techniques, the identification and creation of patterns, the Calibre Pattern Matching process, and the benefits derived from its use.

This paper details how the Calibre xACT 3D extraction solution addresses the extraction challenges for design signoff at advanced nodes.

What Is CFA and Why Do I Need It? This five-part paper series examines the conditions that led to the development of recommended rules, and describes the process by which automated design analysis and rule verification can help designers optimize designs to the fullest and most efficient use of area, while still ensuring manufacturability.

This paper will examine the implementation and demonstrate the benefits of eqDRC through a variety of examples comparing traditional DRC with eqDRC approaches.

Mocana's NanoSSL is a comprehensive SSL solution designed for efficiency and high performance in embedded and resource-constrained environments. Download the NanoSSL whitepaper and receive a free trial.

Learn how Mocana's NanoSSH can speed your product development while providing best-in-class SSH services custom-built for device environments. Download the NanoSSH whitepaper and receive a free trial.

Mocana's NanoVOIP is a comprehensive security solution for application developers and device designers looking to build secure VOIP products. Its simple API means no previous crypto expertise is required, and its tiny memory footprint goes where other implementations simply can't. Download the NanoVOIP whitepaper and receive a free trial.

Learn how Mocana's NanoSec can speed your product development cycle while providing best-in-class device security for resource-constrained environments. Download the product whitepaper and receive a free trial.

Until recently, designing or building a wireless device meant cobbling together whatever security implementations you could find, often with open source and other code that is usually too big and too slow for device environments.

Mocana's NanoCrypto is one of the smallest, fastest, and most complete cryptography engines designed for embedded systems. Download the NanoCrypto whitepaper and receive a free trial.

Today's technological innovation demands high performance coupled with low environmental impact. These dual requirements are driving components of the semiconductor industry which informs many global businesses and consumer lives.

This technology white paper introduces the reader to an entirely new scheme for lossless audio compression called apt-X Lossless.

This paper will present the case that there are a number of frailties associated with Dolby E, the most notable of which are the latency, audio quality and general awkwardness in terms of operation and implementation.

This paper examines the key performance aspects of low bit rate audio codecs for the next generation of bandwidth-efficient digital wireless microphone systems that meet the future needs of live events.

This paper discusses research undertaken to lower the complexity of existing high-quality sub-band ADPCM coding schemes to better satisfy these conflicting criteria.

Viable distribution of Multi-channel Audio-over-IP for Live and Interactive "Voice Talent" based Gaming using High-quality, Low-latency Audio Codec technology.

"As the number of enhancements to various Hardware Description Languages (HDLs) has increased over the past year, so too has the complexity of determining which language is best for a particular design. Many designers and organizations are contemplating whether they should switch from one HDL to another. This paper compares the technical characteristics of three, general-purpose HDLs.

This paper looks at the issues, materials and current processes being researched to create this integrated Opto-Electronic Circuit Board by European, Japanese and North American organizations.

Join us at ESC Boston, September 21-24 at the Hynes Convention Center, in Boston, MA. Expo registration is FREE, and advanced registration pricing is still available for conference packages.

Find out how a robust configuration audit and control system can enable electronic submissions and signatures, and validate electronic data, in compliance with the FDA's mandatory submission of clinical trials records.

No question the UI in electronic devices today is playing a larger role in the success of a device. Get the UI wrong and your product will have little chance of surviving. And it isn’t enough to deliver a UI that is merely functional: it has to look good too. Studies have shown that a good cosmetic design can encourage users to explore the full range of features and often, can engender the perception that a product is easier to use, which can make consumers more tolerant of product deficiencies. Learn more today!

A powerful signal integrity analysis tool must be flexibility, easy to use and integrated into an existing EDA framework and design flow. In addition, it is important for the tool to be accurate enough. This report reviews a validation study for the Mentor Graphics HyperLynx 8.0 PI tool to establish confidence in using it for power integrity analysis.

For advanced signaling over high-loss channels, designs today are using equalization and several new measurement methods to evaluate the performance of the link. Both simulation and measurement tools support equalization and the new measurement methods, but correlation of results throughout the design flow is unclear. In this paper a high performance equalizing serial data link is measured and the performance is compared to that predicted by simulation. Then, the differences between simulation and measurements are discussed as well as methods to correlate the two.

High Density Interconnect (HDI) is being used more often to meet the growing need for more complex designs in smaller form factors. Beyond some of the more obvious electrical effects of using smaller vias, there is also an impact to the power integrity of a board using HDI. This includes different effects of mounted inductances of decoupling capacitors, changes in plane performance due to reduction in perforation from chip pinouts, and the inherent plane-capacitance changes from using dielectrics of various thicknesses. This paper will examine and quantify these effects, using numerous design examples, including a large conventional through-hole design board that was reduced using HDI.