This paper investigates the effects of DDR4ís Pseudo Open Drain (POD) driver on data bus signaling and describes methodologies for dynamically calculating the DRAMís internal VrefDQ level required for data eye analysis.
This white paper discusses the conditions that have created the need for pattern matching techniques, the identification and creation of patterns, the Calibre Pattern Matching process, and the benefits derived from its use.
What Is CFA and Why Do I Need It? This five-part paper series examines the conditions that led to the development of recommended rules, and describes the process by which automated design analysis and rule verification can help designers optimize designs to the fullest and most efficient use of area, while still ensuring manufacturability.
White Paper Published By: Mocana
Published Date: Jun 18, 2010
Mocana's NanoVOIP is a comprehensive security solution for application developers and device designers looking to build secure VOIP products. Its simple API means no previous crypto expertise is required, and its tiny memory footprint goes where other implementations simply can't. Download the NanoVOIP whitepaper and receive a free trial.
The Mechanical Analysis Division of Mentor Graphics (formerly Flomerics) provides the world's most advanced computational fluid dynamics products. Our simulation software and consultancy services eliminate mistakes, reduce costs, and accelerate and optimize designs involving heat transfer and fluid flow before physical prototypes are built.
White Paper Published By: Ramtron
Published Date: Nov 11, 2009
Today's technological innovation demands high performance coupled with low environmental impact. These dual requirements are driving components of the semiconductor industry which informs many global businesses and consumer lives.
White Paper Published By: APTX
Published Date: Nov 05, 2009
This paper will present the case that there are a number of frailties associated with Dolby E, the
most notable of which are the latency, audio quality and general awkwardness in terms of
operation and implementation.
White Paper Published By: APTX
Published Date: Nov 05, 2009
This paper examines the key performance aspects of low bit rate audio codecs for the next generation of bandwidth-efficient digital wireless microphone systems that meet the future needs of live events.
"As the number of enhancements to various Hardware Description Languages (HDLs) has increased over the past year, so too has the complexity of determining which language is best for a particular design. Many designers and organizations are contemplating whether they should switch from one HDL to another.
This paper compares the technical characteristics of three, general-purpose HDLs.
No question the UI in electronic devices today is playing a larger role in the success of a device. Get the UI wrong and your product will have little chance of surviving. And it isn’t enough to deliver a UI that is merely functional: it has to look good too. Studies have shown that a good cosmetic design can encourage users to explore the full range of features and often, can engender the perception that a product is easier to use, which can make consumers more tolerant of product deficiencies. Learn more today!
A powerful signal integrity analysis tool must be flexibility, easy to use and integrated into an existing EDA framework and design flow. In addition, it is important for the tool to be accurate enough. This report reviews a validation study for the Mentor Graphics HyperLynx 8.0 PI tool to establish confidence in using it for power integrity analysis.
For advanced signaling over high-loss channels, designs today are using equalization and several new measurement methods to evaluate the performance of the link. Both simulation and measurement tools support equalization and the new measurement methods, but correlation of results throughout the design flow is unclear. In this paper a high performance equalizing serial data link is measured and the performance is compared to that predicted by simulation. Then, the differences between simulation and measurements are discussed as well as methods to correlate the two.
High Density Interconnect (HDI) is being used more often to meet the growing need for more complex designs in smaller form factors. Beyond some of the more obvious electrical effects of using smaller vias, there is also an impact to the power integrity of a board using HDI. This includes different effects of mounted inductances of decoupling capacitors, changes in plane performance due to reduction in perforation from chip pinouts, and the inherent plane-capacitance changes from using dielectrics of various thicknesses. This paper will examine and quantify these effects, using numerous design examples, including a large conventional through-hole design board that was reduced using HDI.
The success of any consumer electronic device depends to a large extent on the appeal of the user interface (UI) and how easy the device is to use. Studies show that good cosmetic design can encourage users to explore the full range of features and often engenders the perception that a product is easier to use. So if the benefits of a great looking, easy-to-use UI are so clear, why are so many products still falling short of customer expectations? The solution lies in taking a fresh new approach a consumer electronic device UI plays. By identifying common UI functionality and implementing it in a reusable and customizable way, we can make it far easier for embedded engineers to deliver visually engaging and easy-to-use consumer electronic products.
Moving to C++ presents opportunities for higher programmer productivity. The requirements of embedded systems, however, demand that the adoption of C++ be carefully measured for the performance impact of run-time costs present in C++, but not in C. This talk suggests strategies for developers who are starting their acquaintance with C++.
To accommodate increasingly dense technology environments, increasingly critical business applications, and increasingly stringent service level demands, data centers are typically engineered to deliver the highest-affordable availability levels facility-wide. Within this monolithic design approach, the same levels of mechanical, electrical, and IT infrastructure are installed to support systems and applications regardless of their criticality or business risk if unplanned downtime occurs. Typically, high redundancy designs are deployed in order to provide for all eventualities. The result, in many instances, is to unnecessarily drive up both upfront construction or retro-fitting costs and ongoing operating expenses.
Uninterruptible Power Solutions are often solved at the facility level with unnecessarily large, inefficient, expensive and complex AC UPS systems. While this provides an easy demarcation line between the facility and end equipment, with each focusing on a different part of the problem, it also results in overall operating efficiency and total cost of ownership being difficult to ascertain and optimize.
Modern Electronic Systems are quite often powered from a three-phase power source. While utilizing power modules that operate directly from three-phase power might seem to provide optimal simplicity and flexibility, the added complexity required to realize three-phase power factor corrected circuitry usually negates any potential savings.