System On A Chip

This technology white paper introduces the reader to an entirely new scheme for lossless audio compression called apt-X Lossless.

This paper will present the case that there are a number of frailties associated with Dolby E, the most notable of which are the latency, audio quality and general awkwardness in terms of operation and implementation.

This paper examines the key performance aspects of low bit rate audio codecs for the next generation of bandwidth-efficient digital wireless microphone systems that meet the future needs of live events.

This paper discusses research undertaken to lower the complexity of existing high-quality sub-band ADPCM coding schemes to better satisfy these conflicting criteria.

Viable distribution of Multi-channel Audio-over-IP for Live and Interactive "Voice Talent" based Gaming using High-quality, Low-latency Audio Codec technology.

While most coating systems address "piece parts", our linear system maximizes polymer yields, maintains consistent quality, increasing output, thereby driving down piece part costs.

Power distribution units (PDUs) are vital to the management of power to IT arrays and have evolved from a simple panel of switches and outlets to designs that can now be considered "intelligent" through the inclusion of internal processing capabilities.

A methodology to create multiple SoC using limited resources

Using digital control in power supplies is considerably more flexible than analog control in its ability to adapt to changes and digital control inside the power supply results in advantages to the system application such as improved efficiency, fewer external components and reduced overall cost.

An outline of the steps required to reach parallel test execution

Managing SOC verification database by synchronizing system calls

Aspects of functional verification of power aware security architecture

New technologies emerge every day, but not all of them pay off, and adopting them too early might be risky for your organization.

This webcast presents an easy to follow process that you can use to capture requirements and specify a system architecture.

Learn how to balance the positive and negative effects of memory utilization in virtual infrastructures to better handle system workload and priority--while improving server utilization

Offshoring Is a Cost Effective Solution to Your IT Needs

This paper will examine current methods used to eliminate waived errors at the chip level and describe a new automatable method for identifying and removing waived errors from DRC results.

This white paper discusses the conditions that have created the need for pattern matching techniques, the identification and creation of patterns, the Calibre Pattern Matching process, and the benefits derived from its use.

This paper details how the Calibre xACT 3D extraction solution addresses the extraction challenges for design signoff at advanced nodes.

What Is CFA and Why Do I Need It? This five-part paper series examines the conditions that led to the development of recommended rules, and describes the process by which automated design analysis and rule verification can help designers optimize designs to the fullest and most efficient use of area, while still ensuring manufacturability.

This paper will examine the implementation and demonstrate the benefits of eqDRC through a variety of examples comparing traditional DRC with eqDRC approaches.

"As the number of enhancements to various Hardware Description Languages (HDLs) has increased over the past year, so too has the complexity of determining which language is best for a particular design. Many designers and organizations are contemplating whether they should switch from one HDL to another. This paper compares the technical characteristics of three, general-purpose HDLs.

This paper looks at the issues, materials and current processes being researched to create this integrated Opto-Electronic Circuit Board by European, Japanese and North American organizations.

A powerful signal integrity analysis tool must be flexibility, easy to use and integrated into an existing EDA framework and design flow. In addition, it is important for the tool to be accurate enough. This report reviews a validation study for the Mentor Graphics HyperLynx 8.0 PI tool to establish confidence in using it for power integrity analysis.

For advanced signaling over high-loss channels, designs today are using equalization and several new measurement methods to evaluate the performance of the link. Both simulation and measurement tools support equalization and the new measurement methods, but correlation of results throughout the design flow is unclear. In this paper a high performance equalizing serial data link is measured and the performance is compared to that predicted by simulation. Then, the differences between simulation and measurements are discussed as well as methods to correlate the two.