Comparison of VHDL, Verilog and SystemVerilog

Functional Verification White Paper
Comparison of VHDL, Verilog
and SystemVerilog
Stephen BaileyMentor Graphics Corporation
www.mentor.comIntroduction strong typing requires additional coding toexplicitly convert from one data type to anotherAs the number of enhancements to various (integer to bit-vector, for example). Hardware Description Languages (HDLs) hasincreased over the past year, so too has the com- The creators of VHDL emphasized semanticsplexity of determining which language is best for that were unambiguous and designs that werea particular design. Many designers and organi- easily portable from one tool to the next. Hence,zations are contemplating whether they should race conditions, as an artifact of the languageswitch from one HDL to another. and tool implementation, are not a concern forVHDL users. This paper compares the technical characteristicsof three, general-purpose HDLs: Several related standards have been developed toincrease the utility of the language. Any VHDL. VHDL (IEEE-Std 1076): A general-purpose design today depends on at least IEEE-Std 1164digital design language supported by multiple (std_logic type), and many also depend on stan-verification and synthesis (implementation) dard Numeric and Math packages as well. Thetools. development of related standards is due to anoth-. Verilog (IEEE-Std 1364): A general-purpose er goal of VHDL's authors: namely, to produce adigital design language supported by multiple general language and allow development ofverification and synthesis tools. reusable packages to cover functionality notbuilt into the language.. SystemVerilog: An enhanced version ofVerilog. As SystemVerilog is currently being VHDL does not define any simulation control ordefined by Accellera, there is not yet an monitoring capabilities within the language.IEEE standard. These capabilities are tool dependent. Due tothis lack of language-defined simulation controlcommands and also because of VHDL's user-General Characteristics of the Languages defined type capabilities, the VHDL communityEach HDL has its own style and heredity. The usually relies on interactive GUI environmentsfollowing descriptions provide an overall "feel" for debugging design problems.for each language. A table at the end of thepaper provides a more detailed, feature-by-fea- Verilogture comparison. Verilog is a weakly and limited typed language.Its heritage can be traced to the C programmingVHDL language and an older HDL called Hilo.VHDL is a strongly and richly typed language. All data types in Verilog are predefined in theDerived from the Ada programming language, its language. Verilog recognizes that all data typeslanguage requirements make it more verbose have a bit-level representation. The supportedthan Verilog. The additional verbosity is intend- data representations (excluding strings) can beed to make designs self-documenting. Also, the mixed freely in Verilog.
Comparison of VHDL, Verilog, and SystemVerilog 1Simulation semantics in Verilog are more language than Verilog, it provides capabilitiesambiguous than in VHDL. This ambiguity gives for defining and packaging reusable functionalitydesigners more flexibility in applying optimiza- not already included in the language.tions, but it can also (and often does) result in SystemVerilog also adds capabilities targeted atrace conditions if careful coding guidelines are testbench development, assertion-based verifica-not followed. It is possible to have a design that tion, and interface abstraction and packaging. generates different results on different vendors'tools or even on different releases of the samevendor's tool. Pros and Cons of Strong TypingUnlike the creators of VHDL, Verilog's authors The benefit of strong typing is finding bugs in athought that they provided designers everything design as early in the verification process asthey would need in the language. The more lim- possible. Many problems that strong typingited scope of the language combined with the uncover are identified during analysis/compila-lack of packaging capabilities makes it difficult, tion of the source code. And with run-timeif not impossible, to develop reusable functional- checks enabled, more problems may be foundity not already included in the language. during simulation.
Verilog defines a set of basic simulation control The downside of strong typing is performancecapabilities (system tasks) within the language. cost. Compilation ten... [download for more]