Besides faster data rates, the new DDR4 standard incorporates additional changes from prior DDR technologies which impact the board design engineer. New factors in DDR4 such as an asymmetric termination scheme, data bus inversion and signal validation using eye masks require new methods of validating designs through simulation.
This paper investigates the effects of DDR4ís Pseudo Open Drain (POD) driver on data bus signaling and describes methodologies for dynamically calculating the DRAMís internal VrefDQ level required for data eye analysis, methodologies for generating and verifying the data eye as well as ways of incorporating write leveling and calibration into the simulation.
Additionally, evaluation of Simultaneous Switching Noise (SSN) by
incorporation of power integrity effects into the signal integrity analysis is also critical to board design and timing closure and will be elaborated with examples.