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Power Integrity Effects of High Density Interconnect (HDI)

White Paper Published By: Mentor Graphics

High Density Interconnect (HDI) is being used more often to meet the growing need for more complex designs in smaller form factors. Beyond some of the more obvious electrical effects of using smaller vias, there is also an impact to the power integrity of a board using HDI. This includes different effects of mounted inductances of decoupling capacitors, changes in plane performance due to reduction in perforation from chip pinouts, and the inherent plane-capacitance changes from using dielectrics of various thicknesses. This paper will examine and quantify these effects, using numerous design examples, including a large conventional through-hole design board that was reduced using HDI.



Tags : 
power integrity effects, mentor graphics, high density interconnect, hdi, chip pinouts, perforation, multilayer or build-up multilayer, bum

Mentor Graphics
Published:  Apr 03, 2009
Type:  White Paper
Length:  16 pages

White Paper
POWER INTEGRITY EFFECTS OF HIGH DENSITY
INTERCONNECT (HDI)March 2009
ABSTRACTHigh Density Interconnect (HDI) is being used more often to meet the growing need for more complex designsin smaller form factors. Beyond some of the more obvious electrical effects of using smaller vias, there is also animpact to the power integrity of a board using HDI. This includes different effects of mounted inductances ofdecoupling capacitors, changes in plane performance due to reduction in perforation from chip pinouts, and theinherent plane-capacitance changes from using dielectrics of various thicknesses. This paper will examine andquantify these effects, using numerous design examples, including a large conventional through-hole designboard that was reduced using HDI.
Authors:Happy HoldenMentor Graphics Corporation8005 SW Boeckman RoadWilsonville, OR 97070 USA Phone: +1 800-592-2210 or +1 503-685-7000Happy_Holden@mentor.com
Patrick CarrierMentor Graphics Corporation8005 SW Boeckman RoadWilsonville, OR 97070 USA Phone: +1 800-592-2210 or +1 503-685-7000Patrick_Carrier@mentor.com
www.mentor.com/pcbIn order to efficiently interconnect array packages with produced photodielectric vias), and Dr. Walter Schmidthigh numbers of I/Os, a new methodology needed to at Contraves (who developed plasma-etched vias). be developed. Although terms such as SequentialMultilayer or Build-up Multilayer (BUM) have Laser-drilled vias were used in mainframe computersurfaced in the last few years the real benefit of High multilayers in the late 1970s. These were not as smallDensity Interconnects (HDI) is in the small holes as the laser-drilled vias today and were produced onlyidentified as "Microvias". These holes are very small. in FR-4 with great difficulty and at great cost. The firstThe HDI Design Committee of the IPC has identified production build-up or sequential printed boardsmicrovias as any hole equal to or less than 150 appeared in 1984, starting with the Hewlett-Packardmicrons; that's six thousandths of an inch (a.k.a. 6 laser-drilled FINSTRATE computer boards, followedmils). Two basic HDI structures exist; 1. The "build- in 1991 in Japan with Surface Laminar Circuits (SLC)up" or "sequential build-up" structures and 2. The by IBM-YASU and in Switzerland with DYCOstrate"any-layer" structures. by Dyconex.
High Density Interconnect printed circuits actually HDI FABRICATION BASICS started in 1980, when researchers started investigating Figure 1 below shows the breakdown of Sequentialways to reduce the size of vias. The first innovator is Build-Up Technologies (SBU) or High Densitynot known, but some of the earliest pioneers include Interconnects. The three basic elements are DielectricLarry Burgess of MicroPak Laboratories (developer of Format, Via Formation, and Metallization Methods.the LaserVia), Dr. Charles Bauer at Tektronix (who
Figure 1: The process of developing HDI boards (Sequential Buildup) is shows graphically here.
www.mentor.com/pcb 1There are nine different general dielectric materials the existing microvia holes, which become buried viaused in HDI processes. IPC slash sheets like IPC- holes (BVHs).4101B and IPC-4104 cover many of these, but manyare not yet specified by IPC. The materials are: Through-via drilling is possible below 0.20 mm (0.008in.), but cost and practicality discourage this. Below1. Photosensitive Liquid Dielectrics 0.20 mm, laser and other via-formation processes are2. Photosensitive Dry Film Dielectrics more cost-effective. There are seven different methods3. Polyimide Flexible Film of forming the IVHs used in HDI processes. Laser4. Thermally Cured Dry Films drilling is the most prominent, but the other six come5. Thermally Cured Liquid Dielectric into use as well. The methods are:6. Resin Coated Copper Foil (RCC), dual-layer andreinforced 1. Various Laser Drilling Methods including 7. Conventional FR-4 Cores and Prepregs UV-Yag, UV-Eximer and CO28. New 'spread-glass' laser-drillable (LD) Prepregs 2. Mechanical Drilling9. Thermoplastic 3. Photo Process to define vias in photo-dielectricsWhen considering a dielectric, also consider the 4. Plasma Drillingmethod of via formation. Figure 2 below shows 5. Insulation Displacement of Via Pastesdetails of the 10 types of via formations. 6. Photo, Plating and Etch of Solid Vias7. Tool Foil
Figure 2: Methods of via formation (from IPC-2315 and IPC-2226
Although laser via metho... [download for more]

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